September 4, 2020

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Marvell Announces 112G SerDes Built on TSMC 5nm

Marvell Announces 112G SerDes Built on TSMC 5nm

So far we have three products in the market built on TSMCs N5 process: the Huawei Kirin 9000 5G SoC, found in the Mate 40 Pro, the Apple A14 SoC, found in the iPhone 12 family, and the Apple M1 SoC, which is in the new MBA/MBP and Mac Mini. We can now add another to that list, but its not a standard SoC: here we have IP for a SerDes connection, now validated and ready for licensing in TSMC N5. Tod

ay Marvell is announcing its DSP-based 112G SerDes solution for licensing.

Modern chip-to-chip networking infrastructure relies on high speed SerDes connections to enable a variety of different protocols at a range of speeds, typically in Ethernet, fiber optics, storage, and connectivity fabrics. Current high-speed connections rely on 56G connections, and so moving up to 112G enables double the speed. Several companies have 112G IP available, however Marvell is the first to enable it in 5nm, ensure it is hardware validated, and offer it for licensing.

These sorts of connections have a number of measurements to compare them to other 112G solutions: the goal is to not only meet the standard, but offer a solution that uses less power, but also a lower potential error rate, especially for high-speed high-reliability infrastructure applications. Marvell is claiming that its new solution enables a significant power reduction in energy per bit transferred up to 25% compared to equivalent TSMC 7nm offerings, along with tight power/thermal constraints and a 40dB insertion loss.

We typically expect data to travel down a connection like this as a series of ones and zeros, i.e. a 1-bit operation which can be a 0 or a 1, known as NRZ (non-return to zero) - however Marvells solution enables 2-bit operation, such as a 00, 01, 10, or 11, known as PAM4 (Pulse Amplitude Modulation). This enables double the bandwidth, but does require some extra circuitry. PAM4 has been enabled at lower SerDes speeds and at 112G before, but not for TSMC N5. As we move to even faster speeds, PAM4 will become a necessity to enable them. Regular readers may identify that NVIDIAs RTX 3090 uses PAM4 signaling (on N7) to enable over 1000 GB/s of bandwidth with Microns GDDR6X it can also be run in NRZ mode for lower power if needed.

Image from Micron

Marvell says it is already engaged with its custom ASIC customers across multiple markets with the 112G implementation. Alongside the new 112G SerDes, the company says it is set to enable a complete suite of PHYs, switches, DPUs, custom processors, controllers, and accelerators built on 5nm, and that this initial offering is but the first step.

Related Reading

Better Yield on 5nm than 7nm: TSMC Update on Defect Rates for N5
TSMC Boosts CapEx by $1 Billion, Expects N5 Node to Be Major Success
Apple Announces The Apple Silicon M1: Ditching x86 - What to Expect, Based on A14
Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020
Huawei Announces Mate 40 Series: Powered by 15.3bn Transistors 5nm Kirin 9000
Intel Launches Stratix 10 TX: Leveraging EMIB with 58G Transceivers
Intels New 224G PAM4 Transceivers

Author: Dr. Ian Cutress

Date: 2020-11-17


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